Statistical Analysis and Comparison of Optical Classification of Atmospheric Aerosol Lidar Data

This dissertation presents a new study for the analysis and classification of atmospheric aerosols in remote sensing LIDAR data. Information on particle size and associated properties are extracted from these remote sensing atmospheric data which are collected by a ground-based LIDAR system. This study first considers optical LIDAR parameter-based classification methods for clustering and classification of different types of harmful aerosol particles in the atmosphere. Since accurate methods for aerosol prediction behaviors are based upon observed data, computational approaches must overcome design limitations, and also consider appropriate calibration and estimation accuracy. Consequently, two statistical methods based on generalized linear models (GLM) and regression tree techniques are used to further analyze the performance of the LIDAR parameter-based aerosol classification methods. The goal of this part of GLM and regression tree analyses is to compare and contrast distinct classification data schemes, and compare the results with the measured aerosol reflection data in the atmosphere. The detail statistical comparison and analysis show that the optical methods adopted in this study for classification and prediction of various harmful aerosol types such as soot, carbon monoxide (CO), sulfates (SOx) and nitrates (NOx) are effective

FPGA implementation of a frame delay

The objective of this thesis is to investigate the applicability of Field Programmable Gate Arrays (FPGAs) for frame delay implementation. FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fabrication facility. They offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time. Frame delays are easier to realize using R/W memory where data is written into the memory and read out for each frame. FPGAs are used in a Quartus II environment as it is easy to perform frame delay implementation using schematic entry procedure. Since FPGAs use look-up tables as configurable logic blocks, they are considered as an appropriate choice for frame delay based designs